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ACS161MS
January 1996
Radiation Hardened 4-Bit Synchronous Counter
Pinouts
16 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835, DESIGNATOR CDIP2-T16, LEAD FINISH C TOP VIEW
MR 1 CP 2 P0 3 P1 4 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 TE 9 SPE
Features
* Devices QML Qualified in Accordance with MIL-PRF-38535 * Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96706 and Intersil' QM Plan * 1.25 Micron Radiation Hardened SOS CMOS * Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si) * Single Event Upset (SEU) Immunity: <1 x 10 (Typ)
-10
Errors/Bit/Day MEV-cm2/mg
* SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100
P2 5 P3 6 PE 7 GND 8
* Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse * Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse * Latch-Up Free Under Any Conditions * Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC * Significant Power Reduction Compared to ALSTTL Logic * DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V * Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min * Input Current 1A at VOL, VOH * Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ)
16 PIN CERAMIC FLATPACK MIL-STD-1835, DESIGNATOR CDFP4-F16, LEAD FINISH C TOP VIEW
MR CP P0 P1 P2 P3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 TE SPE
Description
The Intersil ACS161MS is a Radiation Hardened 4-Bit Binary Synchronous Counter. The MR is an active low master reset. SPE is an active low Synchronous Parallel Enable which disables counting and allows data at the preset inputs (P0 - P3) to load the counter. CP is the positive edge clock. TC is the terminal count or carry output. Both TE and PE must be high for counting to occur, but are irrelevant to loading. TE low will keep TC low. The ACS161MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic family. The ACS161MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix).
PE GND
Ordering Information
PART NUMBER 5962F9670601VEC 5962F9670601VXC ACS161D/Sample ACS161K/Sample ACS161HMSR TEMPERATURE RANGE -55oC -55oC to to +125oC +125oC SCREENING LEVEL MIL-PRF-38535 Class V MIL-PRF-38535 Class V Sample Sample Die PACKAGE 16 Lead SBDIP 16 Lead Ceramic Flatpack 16 Lead SBDIP 16 Lead Ceramic Flatpack Die
25oC 25oC 25oC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
1
518818 3600.1
ACS161MS Functional Diagram
SPE
CP
J CP K
Q QN CD
Q0
P0
MR J CP P1 K QN CD Q Q1
J CP P2 K
Q QN CD
Q2
J CP K P3
Q QN CD
Q3
PE TC TE
TRUTH TABLE INPUTS OPERATING MODE Reset (Clear) Parallel Load MR L H H Count Inhibit H H H X X CP X PE X X X h I (Note 2) X TE X X X h X I (Note 2) SPE X I I h (Note 3) h (Note 3) h (Note 3) PN X I h X X X
OUTPUTS QN L L H count qN qN TC L L (Note 1) (Note 1) (Note 1) L
H = High Steady State, L = Low Steady State, h = High voltage level one setup time prior to the Low-to-High clock transition, I = Low voltage level one setup time prior to the Low-to-High clock transition, X = Don't Care,q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition, = Low-to-High Transition. NOTES: 1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH). 2. The High-to-Low transition of PE or TE should only occur while ZCP is High for conventional operation. 3. The Low-to-High transition of SPE should only occur while CP is High for conventional operation. 4. The TC output is High when TE is High and the counter is at Terminal Count (HHHH).
Spec Number 2
518818
ACS161MS Die Characteristics
DIE DIMENSIONS: 88 mils x 88 mils 2240mm x 2240mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125kA 1.125kA Metal 2 Thickness: 9kA 1kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: < 2.0 x 105A/cm2 BOND PAD SIZE: 110m x 110m 4.3 mils x 4.3 mils
Metallization Mask Layout
ACS161MS
CP (2) MR (1) VCC (16) TC (15)
P0 (3)
(14) Q0
P1 (4)
(13) Q1
P2 (5)
(12) Q2
P3 (6)
(11) Q3
(7) PE
(8) GND
(9) SPE
(10) TE
Spec Number 3
518818
ACS161MS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Spec Number 4
518818

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